A data processing system may receive data from a plurality of sources.
The application relates to a system for receiving and processing data from a plurality of sources. A message exchange system is provided to allow two or more processors to communicate more efficiently, which may improve input/output (I/O) processing speed.
In an embodiment, the system allows I/O completions to be posted to two memories associated with two processors. Either processor can access an I/O completion notification and prepare the I/O for a subsequent operation.
In an embodiment, the system may use zero-wait-state random access memories (RAMs) to store I/O completion notices from the DMA and messages between processors. The zero-wait-state RAMs reduce RAM access latency. Alternatively, the system may use higher latency RAMs with wait-states to achieve more information capacity at reduced performance.
When a plurality of different sources try to write to a RAM at the same time via a plurality of data paths, the system may overcome the possibility of data corruption by storing data in registers. The system also allows fair and quick access to a plurality of logical partitions in a RAM. Registers also overcome the possibility of data corruption when the RAM is full and a source tries to continue writing to the RAM.
The system may be configured to handle I/O completions that originate from different clock domains. For example, two I/O completions may come from a peripheral component interface (PCI) side, which may be running at 33 MHz, 66 MHz or 133 MHz. Two I/O completions may come from a Fibre Channel Link side, which may be synchronized to 106 MHz or 200 MHz clocks. And an ARM processor may post an I/O completion or inter-processor message with a 200 MHz clock.
The system may keep track of an empty or full status of a RAM and how many locations are filled in the RAM.
In addition, the system may also use door bell registers to notify a processor about important events. The door bell registers allow a first processor to set a particular door bell bit and allow a second processor to read and clear the particular door bell bit. The first processor may also be able to generate an interrupt when a particular door bell bit is set by the second processor.
The system may be implemented in an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) device.
An aspect of the application relates to a system comprising a first channel and a second channel. The first channel comprises a first direct memory access (DMA) engine, a second DMA engine, a first random access memory (RAM) and a first processor. The second channel comprises a third DMA engine, a fourth DMA engine, a second RAM and a second processor.
Another aspect relates to a channel comprising a random access memory, first and second engines and a processor. The random access memory is configured to store input/output completions. The first and second engines are configured to send input/output completions to the random access memory. The processor is configured to process the input/output completions stored in the random access memory.
Another aspect relates to a method comprising: configuring a random access memory (RAM) of a first channel to store input/output (I/O) completions from an engine in a second channel; and processing I/O completions in the RAM of the first channel.
Another aspect relates to a method comprising: detecting whether an engine of a first channel is inactive; if the engine of the first channel is inactive, storing input/output (I/O) completions from an engine in a second channel to a random access memory of the first channel; and processing the I/O completions in the random access memory of the first channel.
Another aspect relates to a method comprising: receiving input/output (I/O) completions from a plurality of data paths; storing the I/O completions in a plurality of registers, each register being configured to store an I/O completion from a predetermined data path; and transferring the I/O completions from the registers to a plurality of logical blocks of a random access memory, each logical block being configured to store I/O completions from a predetermined data path.
The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.